This invention relates to an IC test apparatus wherein the output from a driver drives input and output (referred to simply as "I/O" hereinafter) pins of IC elements to be tested (referred to simply as "test IC elements" hereinafter) and wherein the output signals from individual I/O pins are sent to separate comparators.
Since testing of a large IC element requires a long time, simultaneous testing of more than one IC element is often considered from the standpoint of efficiency. For example, to test the memory IC element pins exclusive for input use, one driver is employed to drive each input pin of every one of the total 128 memory IC elements on a board. This testing system tests 128 elements at a time, thereby reducing the test time equivalent to one hundred and twenty eighth.
The conventional system described above is, however, not applicable to IC elements having pins for both input and output use. Referring to FIG. 1, even when the I/O status of an IC element is controlled at I/O pin by sending I/O signal IOD to more than one test IC element 12.sub.l .about.12.sub.n n so that a test pattern data may be provided from one driver 11 to the input of individual I/O pins corresponding to the test IC elements 12.sub.l .about.12.sub.n and the outputs at individual I/O pins may be supplied to individual comparators 13.sub.l .about.13.sub.n corresponding to each of the test IC elements 12.sub.l .about.12.sub.n, the separate comparison of output from individual IC elements 12.sub.l .about.12.sub.n would be impossible because all the I/O pins on the test IC elements 12.sub.l .about.12.sub.n are interconnected.
Therefore, a prior art carried the simultaneous testing of these test IC elements 12.sub.l .about.12.sub.n by setting separate pairs of driver and comparator for each test IC element of 12.sub.l .about.12.sub.n and by giving the same test pattern to the same pin number on different IC elements each time.
Alternatively, a prior art carried out testing of IC elements one at a time, as illustrated in FIG. 2, by connecting the I/O pins of the same pin number on test IC elements 12.sub.l .about.12.sub.n with the output of common driver 11 and the input of common comparator 13 and by controlling separately the chip selection terminal CS on the test IC elements 12.sub.l .about.12.sub.n using the corresponding drivers 14.sub.l .about.14.sub.n and by sequentially setting the test IC elements 12.sub.l .about.12.sub.n to the enable state.
When every I/O pin of each test IC element is connected to an independent driver-comparator pair, the time required for the simultaneous testing of 128 IC elements, for example, will be shortened to one hundred and twenty eighth of the time needed for sequential testing. However, this system requires numerous drivers. For instance, 512 drivers are needed to test 128 IC elements having a 4M.times.4 memory capacity. Thus, a serious problem is raised if the hardware scale is enlarged significantly. Furthermore, the system shown in FIG. 2 can not shorten the test time.